What Is A Silicon Wafer Used For?

Silicon wafers are made from a single crystal of highly pure silicon, typically with less than one part per billion of contaminants. The Czochralski process is the most common method of forming large crystals of this purity, which involves pulling a seed crystal from molten silicon, commonly known as a melt. The seed crystal is then formed into a cylindrical ingot known as a boule.

Elements such as boron and phosphorus may be added to the boule in precise quantities to control the wafer’s electrical properties, generally for the purpose of making it an n-type or p-type semiconductor. The boule is then cut into thin slices with a wire saw also known as a wafer saw. The cut wafers may be polished to varying degrees.

What Is A Silicon Wafer Used For?

A silicon wafer is a thin slice of crystalline silicon commonly used in the electronics industry. Silicon is used for this purpose because it’s a semiconductor, meaning it’s neither a strong conductor nor strong insulator of electricity. Its natural abundance and other properties generally make silicon preferable to other semiconductors such as germanium for making wafers.

The most common dimensions of silicon wafers depend on their application. The wafers used in ICs are round with diameters typically ranging from 100 to 300 millimeters (mm). The thickness generally increases with the diameter and is usually in the range of 525 to 775 microns (μm). The wafers in solar cells are usually square with sides measuring 100 to 200 mm. Their thickness is between 200 and 300 μm, although this is expected to be standardized to 160 μm in the near future.

Integrated Circuits

An IC, also known as a microchip or just chip, is a set of electronic circuits set into a substrate of semiconducting material. Monocrystalline silicon is currently the most common substrate for ICs, although gallium arsenide is used in some applications such as wireless communication devices. Wafers made of silicon-germanium alloys are also becoming more widely used, typically in applications where the greater speed of silicon-germanium is worth the higher cost.

ICs are currently used in most electronic devices, having virtually replaced separate electronic components. They’re smaller, faster and cheaper to manufacture than discrete components by orders of magnitude. The rapid adoption of ICs in the electronics industry is also due to the modular design of ICs, which easily lends itself to mass production.

Random-access memory (RAM) chips are one of the most common types of ICs, due to their particular need for a high transistor density. The thickness of the layers of photolithographic material in a RAM chip has been shrinking steadily and are now much thinner than the width of the device itself.

These layers are developed in a similar manner to regular photographs except that ultraviolet light is used rather than visible light since the wavelengths of visible light are too large to create features with the necessary precision. The features of modern ICs are so small that process engineers must use electron microscopes to debug them.

Virginia Semiconductor is a manufacturer of Si wafers in the USA. A variety of in-stock standard sizes are available, but we also fulfill a lengthy list of custom wafer specifications. Buy Si wafers online, or contact us with your specification for a quote.

IC Fabrication

Automated test equipment (ATE) tests each wafer before using it to make an IC, a process, commonly known as wafer probing or wafer testing. The wafer is then cut into rectangular pieces known as dies and then connected to an electronic package via electrically conductive wires, which are usually made of gold or aluminum. These wires are bonded to pads that are typically located around the edge of the die using ultrasound in a process called thermosonic bonding.

The resulting devices undergo final testing phases, which typically use ATE and industrial computed tomography (CT) scanning equipment. The relative cost of testing varies greatly according to the yield, size and cost of the device. For example, testing may account for over 25% of the total fabrication costs inexpensive devices, but it can be virtually negligible for large, expensive devices with low yields.


The fabrication of ICs is a highly automated process that uses many specific techniques. These capabilities drive the high cost of building a fabrication facility, which can exceed $8 billion as of 2016. This cost is expected to increase much more quickly than inflation due to the continuing need for greater automation.

The trend towards smaller transistors will continue for the foreseeable future, with 14 nm being state of the art in 2016. IC manufacturers such as Intel, Samsung, Global Foundries and TSMC are expected to begin the transition to 10 nm transistors by the end of 2017.

Large wafers provide an economy of scale, which reduces the total cost of ICs. The largest wafers commercially available are 300 mm in diameter, with 450 mm expected to be the next maximum size. However, significant technical challenges still exist for making wafers of this size.

Additional techniques used in the fabrication of ICs include tri-gate transistors, which Intel has manufactured with a width of 22 nm since 2011. IBM uses a process known as strained silicon directly on insulator (SSDOI), which removes the silicon-germanium layer from a wafer.

Copper is replacing aluminum interconnects in ICs, primarily due to its greater electrical conductivity. Low-K dielectric insulators and Silicon on Insulators (SOIs) are also advanced manufacturing techniques for ICs.


Other Resources About Semiconductors

Basic Wafer Terms & Definitions
Cutting Si Wafers Off-Axis
Oxygen Precipitation in Silicon
Properties of Glass as Related to Applications with Silicon
A Guide to SEMI Specifications for Si Wafers
Wet-Chemical Etching and Cleaning of Silicon


Solar Cells

A solar cell uses the photovoltaic effect to convert light energy into electrical energy, which generally involves the absorption of light by some material to excite electrons into a higher energy state. It’s a type of photoelectric cell, a device that changes its electrical characteristics when exposed to light. Solar cells can use light from any source, even though the term “solar” implies they require sunlight.

The generation of electricity as an energy source is one of the most well-known applications for solar cells. These types of solar cells use a light source to charge a battery, which can be used to power an electrical device.

Solar cells are often integrated into the device they’re intended to power. For example, the solar-powered lights commonly available in home improvement stores use solar cells to charge a battery during the day. At night, the battery powers a motion sensor that turns the light on when it detects motion.

Solar cells may be classified into first, second and third generation types. First generation cells are composed of crystalline silicon, including monocrystalline silicon and polysilicon. They’re currently the most common type of solar cell. Second generation cells use thin film composed of amorphous silicon and are typically used in commercial power stations. Third-generation solar cells use thin film developed with a variety of emerging technologies and currently have limited commercial applications.

Solar Cell Fabrication

The great majority of a first-generation solar cell is composed of crystalline silicon, although its structural quality and purity are far below that used in ICs. Monocrystalline silicon converts light into electricity more efficiently than polysilicon, but monocrystalline silicon is also more expensive.

The wafers are cut into squares to form individual cells, and their corners are then clipped to form octagons. This shape gives solar panels their distinctive diamond-like appearance. The cells that make up a solar panel must all be oriented along the same plane to maximize conversion efficiency. The panels are typically covered with a sheet of glass on the side that faces the sun to protect the wafers.

Solar cells may be connected in series or parallel, depending on specific requirements. Connecting the cells in a series increases their voltage while connecting them in parallel increases the current. The primary disadvantage of parallel strings is that shadow effects can cause the shadowed strings to shut down, which can cause the illuminated strings to apply a reverse bias to the shadowed strings. This effect can result in a substantial loss of power and even damage to the cells.

The preferred solution to this problem is to connect strings of cells in series to form modules and use maximum power point trackers (MPPTs) to handle the power requirements of the strings independently of each other. However, the modules can also be interconnected to form an array with the desired loading current and peak voltage. Another solution to the problems caused by shadow effects is the use of shunt diodes to reduce power loss.

Size Increase

The trend towards larger boules in the semiconductor industry has resulted in an increase in the size of solar cells. The solar panels developed in the 1980s are made of cells with a diameter between 50 and 100 mm. Panels made during the 1990s and 2000s typically used wafers with a diameter of 125 mm, and panels made since 2008 have 156 mm cells.

The Use Of Silicon Wafers

Silicon wafers are most often used as the substrate for integrated circuits (ICs), although they’re also a major component in photovoltaic, or solar, cells. The basic process of fabricating these wafers is the same for both of these applications, although the quality requirements are much higher for the wafers used in ICs. These wafers also undergo additional steps such as ion implantation, etching and photolithographic patterning, which aren’t needed for solar cells.

For more information on silicon wafers, contact Virginia Semiconductor online or at 540.373.2900.


Silicon On Insulator – SOI Wafers: The Basics

Silicon on insulator (SOI) technology is the use of an insulating layer between the silicon substrate and an upper layer of silicon in silicon wafers. Its primary purpose is to improve performance over conventional silicon substrates by reducing electrical losses.

The insulator is usually silicon dioxide or sapphire, which is primarily aluminum oxide with metal impurities. SOI wafers that use sapphire as the insulator may be known more specifically as silicon on sapphire (SOS).

The best insulator in an SOI wafer depends on the intended application, with silicon dioxide being most common in microelectronics due to its ability to reduce short-channel effects.

Sapphire is used more often in radiation-sensitive applications such as high-performance radio frequency (RF) applications. The ideal thickness of the insulating and upper silicon layers in SOI wafers also vary according to application.

How are SOI wafers manufactured?

SOI substrates are generally compatible with conventional fabrication processes, so an SOI process can be implemented without purchasing additional equipment or significantly retooling an existing factory.

The most significant challenges in SOI manufacture include maintaining the thickness of the buried oxide (BOX) layer within a very narrow range and preventing the differential stress in the upper silicon layer from exceeding design limitations.

The transistor’s threshold voltage is also a critical concern in SOI design, since it depends on factors such as the voltage applied to the device and its operational history.

The primary barrier to adoption of SOI devices has historically been the increase of substrate costs, according to IBM. Silicon dioxide-based SOI wafers can be manufactured with several distinct techniques, including Separation by Implantation of Oxygen (SIMOX), wafer bonding and seed methods.

Wafer bonding

Wafer bonding is a packaging technology for microelectronics and similar devices, including microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS) and optoelectronics.

It bonds the silicon dioxide layer directly to the upper silicon layer, most of which is later removed. Various specific wafer-bonding techniques are currently used, including the Smart Cut method used by Soitec.

This method uses ion implantation to create the silicon dioxide layer under the wafer’s surface and exfoliation to control the thickness of the upper silicon layer. Silicon Genesis Corporation uses a technology called NanoCleave that stresses the interface between a silicon layer and a layer of silicon-germanium alloy to separate the silicon layer.

A wafer bond is intended to create a mechanically stable hermetic seal over the wafer that protects it from water vapor and foreign objects. These bonds must therefore be evaluated according to their strength and hermeticity, which may be destructive or nondestructive.

Destructive techniques require sampling and typically involve tensile or shear testing. Other forms of destructive testing include subjecting the wafers to a carefully chosen atmosphere and pressure. Nondestructive testing usually consists of using optical methods to inspect the wafers for cracks or interfacial voids.

The diameter of a bonded wafer typically ranges from about 50 millimeters (mm) to 150mm. The thickness of the wafer is between 10 microns (µm) and 2,000 µm, with a tolerance between 1 and 25 µm.

The thickness of the silicon dioxide layer ranges from 0.5 to 4 µm, and the thickness of the wafer handle is between 100 µm and 2,000 µm. The electrical resistivity of the wafer and handle is between 0.00055 and 10,000 ohm-cm. Bonded wafers may have any crystal orientation and use any dopant.


SIMOX (Separation by Implantation of Oxygen) uses ion implantation to add oxygen ions into the substrate, according to U.S. Patent 5,061,642 and U.S. Patent 5,888,297.

Ion implantation involves accelerating ions into a solid target at low temperature, which alters the chemical and physical properties of the target. In the case of wafer fabrication, the oxygen ions combine with the silicon atoms in the substrate to form silicon dioxide. The concentration of oxygen ions determines the electrical conductivity of the substrate.

The SIMOX follows ion implantation with annealing at high temperature. Annealing involves heating the substrate to slightly above silicon’s recrystallization temperature for a specific period of time and allowing it to cool in a controlled manner. This process creates a layer of silicon dioxide under the substrate’s surface, which is the insulating layer of the SIO structure.

Seed methods

U.S. Patent 5,417,180 describes a seed method of producing SOI wafers, which generally involves growing the upper silicon layer directly onto the insulator.

Seed methods require a template to ensure the silicon is deposited onto the insulator evenly, a process scientifically as homoepitaxy. Techniques for achieving homoepitaxy include using an insulator with the appropriate crystalline orientation and treating the insulator chemically.

SOI device types

An SOI metal–oxide–semiconductor field-effect transistor (MOSFET) has a semiconductor layer on top of an insulator layer. U.S Patent 6,835,633 describes a structure that uses silicon as the semiconductor and a BOX inside a semiconductor layer as the insulator.

SOI MOSFET devices are primarily used by the computer industry, especially in static random access memory (SRAM) chips. SOI MOSFET devices may be classified into fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) types.

FDSOI MOSFETs use a very thin p-type film between the gate oxide (GOX) and BOX, so the depleted region covers the entire film. The GOX is less depleted than the rest of the MOSFET, which increases switching speed due to the increase in inversion charges.

PDSOI devices use a thicker film between the GOX and BOX, which prevents the depleted region from covering the whole film. This characteristic causes PDSOI MOSFETs to behave more like bulk MOSFETS than FDSOI MOSFETs.

The BOX’s depletion charge suppresses the capacitance of the depleted region, substantially reducing the subthreshold swing. This effect lowers a FDSOI MOSFETs gate bias, which reduces its power requirements. Numerical simulations show the minimum theoretical subthreshold swing of these devices to be 60 millivolts (mV) per decade, which MOSFETs can currently achieve.

The BOX in a FDSOI MOSFET prevents the source and drain electric fields from interfering with each other, which provide other advantages over bulk MOSFETs such as reduced threshold voltage roll off. However, the fact that the film isn’t connected to any of the MOSFET’s supplies creates a floating body effect (FBE).

This phenomenon means that the MOSFET’s body forms a capacitor against the insulating layer, causing an accumulated charge that can create adverse effects such as off-state current leakage.

Benefits of applying SOI technology

SOI technology is one of many strategies that wafer manufacturers are using to continue the miniaturization of microelectronic devices. This trend is embodied in Moore’s Law, which holds that the number of transistors in an integrated circuit (IC) doubles about every two years.

The specific benefits of SOI technology over conventional silicon include a lower parasitic capacitance due to the upper silicon’s insulation from the bulk silicon substrate, which reduces power consumption.

Parasitic capacitance, also known as stray capacitance, is a capacitance that occurs between the parts of an electronic component due to their close proximity. It’s generally undesirable, as it causes circuit elements to deviate from their ideal electrical behavior.

The isolation of the upper silicon layer from the substrate in an SOI wafer increases its resistance to latchup, which is a type of low-impedance short circuit. Latchup occurs between a MOSFET’s power supply rails, resulting in a disruption of power or even damage to the MOSFET. It also requires a power cycle to correct.

SOI wafers have greater resistance to radiation, making them less prone to soft errors. The insulating layer also reduces current leakage, which increases their power efficiency.

The higher density also increases the yield, thus improving wafer utilization. Additional advantages of SOI wafers include a reduced dependency on temperature and fewer antenna issues.

Applications for SOI wafers

The applications for SOI wafers include microelectronics, radio frequency (RF) and photonics.


The most common use of SOI wafers is in electronics. The first example of this application occurred in 2000, when IBM implemented SOI in its RS64-IV PowerPC-AS microprocessor, commonly known as “Istar.” AMD has made regular use of SOI technology in its processors since 2001, including its 32nm, 45nm, 65nm, 90nm and 130nm processors.

These processors are available in single, dual, quad, six and eight cores. Freescale also adopted SOI technology for its PowerPC 7455 CPU in 2001, and its current SOI products include its 45nm, 90nm, 130nm and 180nm CPUs.

SOI is also becoming popular in video game consoles, especially those using the 90nm Power Architecture processors. These CPUs are used in a range of consoles, including Microsoft’s Xbox 360, Sony’s Playstation 3 and Nintendo’s Wii. Researchers at Intel built a silicon rib waveguide Raman laser in 2005 that used a single SOI CPU.

However, Intel’s commercial CPUs continue use conventional complementary metal–oxide–semiconductor (CMOS) technology by improving performance through advancements such as High-K Metal Gate (HKMG) and Tri-gate transistors.

RF Applications

Peregrine Semiconductor began developing SOI technology for high-performance RF applications in 1990, and its patented SOS process is now widely used. This device essentially consists of a conventional 0.5 μm CMOS with a sapphire substrate.

The primary benefits of an insulating sapphire substrate in RF applications include improved isolation and tolerance for electrostatic discharge (ESD). Other companies also use SOI technology for RF applications such as cellular radios and smartphones.


Silicon Photonics: An Introduction by Graham T. Reed and Andrew P. Knights describes the wide use of SOI wafers in photonics, which is the study of the generation, detection and manipulation of light.

These wafers are used in optical devices such as waveguides such that the insulating layer allows infrared light from internal reflection to propagate through the silicon layer. The surface of the waveguide is often left uncovered, allowing this infrared light to be detected by a sensor. It may also be covered, usually with a silica cladding.
For more information on SOI wafers or other silicon wafer products, contact us online or call us at 540-373-2900.

Other Resources About Semiconductors

Basic Wafer Terms & Definitions
Cutting Si Wafers Off-Axis
Oxygen Precipitation in Silicon
Properties of Glass as Related to Applications with Silicon
A Guide to SEMI Specifications for Si Wafers
Wet-Chemical Etching and Cleaning of Silicon

How Much Does A Silicon Wafer Cost

A silicon wafer is a thin slice of crystalline silicon, which serves as a substrate for microelectronic devices. It’s most commonly used in the manufacture of integrated circuits (ICs), but wafers are also used to make solar cells.

The fabrication process of a silicon wafer involves many complex steps, including the formation of the crystal, deposition of various materials and photolithographic patterning. The completed microcircuits must also be separated and packaged for sale.

Wafers must be of extremely high quality for an IC to perform effectively, which is the primary factor for their cost. The following steps have the greatest effect on the cost of a silicon wafer:

  • Size
  • Growth method
  • Doping
  • Planar orientation

Size Of Silicon Wafers

Silicon wafers are round, with diameters ranging from 25.4 millimeters (mm) to 300 mm, according to The Facilities 450mm Consortium. The exact measurements of the wafers are in millimeters, although they’re commonly referred to by their closest measurement in inches.

For example, a wafer with a diameter of 25.4 mm across is almost exactly one inch across and is referred to as a “one-inch” wafer. A 300-mm wafer has a diameter of about 11.8 inches and is known as a “12-inch” wafer. Fabrication plants, or fabs, are known by the size of the wafers they produce, as in a “12-inch fab.”

The manufacture of larger wafers has greater throughput, which reduces its cost per die. The silicon wafer industry is therefore strongly motivated to increase the size of its wafers.

The 12-inch wafer is currently state of the art, which replaced the 8-inch wafer as the largest commercially available size beginning in 2000. This transition reduced the cost per die of wafers by 30-40 percent. Companies such as Intel, Samsung and TSMC are currently researching methods of manufacturing an 18-inch wafer, although this size still presents significant technical challenges.

Silicon wafers also become thicker as their surface area increases since they must support their own weight during handling without cracking. The thickness of a wafer ranges from a minimum of 250 microns (µm) for a one-inch wafer to 775 µm for a 12-inch wafer. The increased thickness also contributes to the increased cost of larger wafers.

The Impact Of Die Counts On Silicon Wafer Costs

Manufacturers need to maximize the number of complete dies that a wafer can make to minimize the cost per die.

This goal presents a complex computational problem, since wafers are round and dies are rectangular. This difference in shape results in a number of incomplete dies at the edge of the wafer, which can’t be sold as a functional part.

The maximum die count of a wafer depends on factors such as the aspect ratio of the dies, the width of the scribe lines separating the dies and the space required by test structures.

Formulas for estimating the gross die per wafer (DPW) can account for the wafer area lost to incomplete dies, but not the additional losses resulting from defects and parametric problems.

The formula DPW=[πd^2/(4S)] provides a first-order approximation of the number of dies that a wafer will produce, where DPW is the number of wafers, d is the wafer diameter and S is the width of the dies. This formula simply provides the ratio of the wafer’s surface area to the die’s surface area, so it doesn’t account for incomplete dies.

Higher order approximations like the following use a correction factor to estimate the number of complete dies that a wafer will actually produce:

How Size Impacts Wafer Costs

The total cost of making a wafer increases with its size, although its cost per unit surface area decreases. This relationship means that larger wafers reduce the price of the dies.

The retail price of a basic one-inch silicon wafer without any special features is about $21 when purchased in quantity. A bulk purchase of similar 6-inch silicon wafers costs about $125 per unit, which is about 6 times the price of the one-inch wafer.

However, the surface area of the six-inch wafer is about 36 times greater than that of the one-inch wafer. The cost of dies made from the six-inch wafers will therefore be one sixth that of dies made from the one-inch wafer, all other factors being equal. This result clearly illustrates the financial incentive for increasing wafer sizes.

Growth Method For Silicon Wafers

Wafers are composed of virtually pure crystalline silicon. The commercial processes for forming crystalline silicon include the Czochralski process and the float-zone method, although the Czochralski process is much more common.

Czochralski Process

Microelectronic Materials and Processes reports that the Czochralski process involves pulling a seed crystal from the molten silicon, or “melt,” to form a cylindrical ingot of crystalline silicon known as a boule.

Highly pure silicon is melted in a crucible at about 1,425 degrees Celsius, which is just about silicon’s melting point of 1,414 degrees Celsius.

This process requires an inert environment to prevent chemical reactions in the melt, so the Czochralski process is typically performed in an atmosphere composed inert gas such as silicon. The crucible must also be made of an inert material such as quartz, which is highly stable.

A seed crystal is mounted on a rod and precisely oriented before dipping it into the melt. The rod is then pulled up and rotated simultaneously to extract an ingot from the melt.

The Czochralski process requires a high degree of control over factors such as temperature, pulling speed and rotation speed to avoid instabilities in the ingot during the growth process.

Float Zone Process

The float zone process, also known as vertical zone melting, uses a vertical configuration of silicon that has enough surface tension to prevent the charge from melting. A rod of extremely pure crystalline silicon is passed through a radio-frequency (RF) heating coil to create a small area of molten silicon.

A seed crystal is placed at one end of this zone. The molten zone carries impurities away since most impurities are more soluble in molten silicon than crystalline silicon. This process is carried out in an inert environment like the Czochralski process.

The float zone method eliminates the need for a containment vessel, which is a common source of contamination. The silicon obtained with this method therefore has a lower concentration of impurities than that yielded by the Czochralski process, especially light contaminants such as carbon and oxygen.

Nitrogen is a light impurity that’s now intentionally introduced to float zone silicon for the purpose of controlling micro-defects and increase its mechanical strength.

The primary disadvantage of the float zone method is that it can’t produce wafers larger than six inches due to limitations imposed by the silicon’s surface tension. This method is therefore less commercially useful than the Czochralski process, despite the greater purity of the silicon.

How Growth Method Impacts Wafer Costs

The float zone method is only used for specific applications where a higher purity requirement offsets the limitations on wafer size. The limited use of float zone silicon significantly increases the cost of wafers made with this method.

For example, a basic 6-inch wafer made with the float zone method costs about $60 when purchased in bulk. In comparison, a bulk purchase of similar wafers made with the Czochralski process costs about $29.

Silicon Wafer Doping

Additional elements can be added to the molten silicon in precise quantities to control the electrical properties of a silicon wafer.

Phosphorus is the most common dopant used to make n-type semiconductors, while boron is typically used for p-type semiconductors. Arsenic and antimony are also used to dope silicon wafers.

The concentration of dopant is typically between 10^13 and 10^16 atoms per cubic centimeter of silicon, according to Technology of Integrated Circuit. A cubic centimeter of crystallized silicon contains about 5×10^22 atoms, so a doped silicon wafer is still more than 99.9999% pure.

Oxygen may also be added to the melt to occupy spaces outside the regular crystal lattices, which strengthens the crystal.

While the impurities in a wafer must be kept low in general, metal impurities are of particular concern since they conduct electricity. For example, the concentration of transition metals must be kept below a few parts per billion.

The Impact Of Doping On Wafer Costs

The effect of dopants on the price of a silicon wafer is quite small, compared with other factors. An undoped four-inch wafer with a thickness of about 500 µm has a unit cost of $29 for bulk purchases.

The same wafer costs about $32 when doped with boron. A wafer that’s doped with phosphorus actually costs less, with a unit cost of $27.

Planar Orientation Of Silicon Wafers

The lattice of crystalline silicon may be aligned in several ways when it’s sliced into wafers. These crystal orientations are described by the Miller index, which uses three integers to determine the crystal’s family of lattice planes. The orientations and are the most common for silicon wafers, according to Handbook of Semiconductor Silicon Technology.

Planar orientation is important in wafers because a crystal’s electrical and structural properties are highly anisotropic, meaning they’re dependent upon orientation.

This is particularly true of ion implantation depths, since each planar direction provides distinct paths for transplanting ions.

Orientation is also a critical factor for cutting, or dicing, the wafer. The wafer must be scored along a cleavage plane, so it can be diced into individual dies.

The Impact Of Planar Orientation On Price

Undoped wafers usually have an orientation of , while wafers with an orientation of are primarily used for doping. Doped wafers with an orientation of often cost slightly less, all other factors being equal.

For example, a four-inch wafer with a thickness of 500 µm and a resistivity of 0.0006 ohm-meters costs about $45, while a similar wafer costs only $40.

Have More Silicon Wafer Cost Questions?

Virginia Semiconductor is a fully integrated silicon wafer manufacturer. We have been making wafers from scratch since 1997, allowing us to easily repeat specifications from batch to batch. For 20 years, we have been the world’s number one online source for silicon wafers and substrates.

If you have any additional questions about costs or other silicon wafer related inquiries, contact us online here or call us at 540.373.2900.

Other Resources About Semiconductors

Basic Wafer Terms & Definitions
Cutting Si Wafers Off-Axis
Oxygen Precipitation in Silicon
Properties of Glass as Related to Applications with Silicon
A Guide to SEMI Specifications for Si Wafers
Wet-Chemical Etching and Cleaning of Silicon

Silicon Wafer Properties Explained

A silicon wafer, also known as a slice or substrate, is a thin slice of crystalline silicon. It’s primarily used as the substrate for integrated circuits (ICs) since silicon is a highly stable semiconductor.

The crystal used to make wafers must be more than 99.9999999% pure silicon, which presents significantly technical challenges in their manufacture.

The Czochralski process is the most common method for growing highly pure crystals made of semiconductors such as silicon and germanium: The silicon is melted under sterile conditions, and other elements known as dopants are often added to the molten silicon, or melt.

A seed crystal is then pulled from the melt and formed into a cylindrical ingot known as a boule, according to Microelectronic Materials and Processes. After the boule cools, it’s sliced into wafers with a wire saw, commonly known as a wafer saw. The wafers are cleaned with a series of weak acids to remove contaminants and repair damage caused by the wafer saw.

A particular application requires a wafer to have very specific properties. Buyers must therefore consider a variety of properties when selecting a batch of silicon wafers, including the following:

  • Size
  • Die count
  • Orientation
  • Dopants

Silicon Wafer Size

The number of chips that a wafer can produce is proportional to its surface area, but its fabrication cost increases more slowly than the surface area. The wafer industry therefore has a strong financial incentive to make the largest wafers that are commercially practical, especially considering the small size and high value of ICs.

Wafer size has continued to increase, with a diameter of 300 millimeters (mm) being the current maximum. The transition from 200mm to 300mm wafers on a commercial scale began in 2000, and reduced the cost per die by 30 to 40 percent.

However, this change required the wafer industry to overcome significant technical challenges and a large investment in new infrastructure.

We have also published a list of common silicon wafer terms and definitions if you need more background on some of the language used in this article.

Diameter Of Silicon Wafers

Wafers are round, with diameters ranging from 25mm to 300mm. F450C reports that the following sizes are currently available:

  • 25mm
  • 51mm
  • 76mm
  • 100mm
  • 130mm
  • 150mm
  • 200mm
  • 300mm
  • 450mm

Wafers are commonly known by their diameter to the nearest inch, even though they’re measured in millimeters.

For example, a wafer with a diameter of 300 mm is known as a “12-inch wafer,” although its actual diameter is only about 11.8 inches.

Likewise, a semiconductor fabrication plant, or fab, is also known by the diameter of its wafers to the nearest inch. A fab that makes 300-mm wafers is therefore known as a “12-inch plant.”

Wafer Thickness

A larger wafer must be thicker, since it must support its own weight without cracking during handling. However, the increase in thickness is significantly less than the increase in diameter.

For example, a one-inch wafer is typically about 250 microns (µm) thick, while the thickness of a 12-inch wafer is about 775 µm. Despite being almost 12 times wider than the one-inch wafer, a 12-inch wafer is only slightly more than three times thicker.

Transition to 18-Inch Wafers

The next size for wafers is expected to be 450mm, or about 18 inches, although considerable debate currently exists as to if and when this change might occur.

EE Times reported in 2008 that Intel, TSMC and Samsung were each conducting independent research on making their own prototypes for an 18-inch wafer. However, no manufacturer has yet produced a commercially viable wafer of this size as of 2017.

Lithographer Chris Mack stated in a 2012 interview published in Semiconductor Engineering that 450mm wafers would only reduce the cost per die of 300mm wafers by 10 to 20 percent.

Mack argues that the primary reason for such a modest decrease is that the majority of wafer processing costs are due to lithography rather than the manufacture of the wafer itself.

Lithography doesn’t provide the scalability that increasing wafer size does because lithography costs are related to surface area more than wafer count.

Increasing the diameter size improves a fab’s throughput, which ultimately reduces the cost of the ICs made from those wafers. Despite the productivity improvement, semiconductor manufacturers have significant concerns about receiving an adequate return on their investment in new fabrication equipment.

The change from 8-inch to 12-inch wafers required a major investment that had to be made during the economic downturn caused by the dot-com bubble burst in 2000.

While 8-inch fabs only need to be partially automated, 12-inch fabs must be fully automated. An 18-inch fab will require similar retooling, meaning only some of the existing equipment can be used for the new wafer size.

Furthermore, larger wafers incur additional processing costs. The ingots for 18-inch wafers will weigh 3X more than the ingots for 12-inch wafers, so they’ll need to spend 3X longer cooling on the ramp.

The timeline for the transition to 18 inches is currently uncertain, but many industry experts are convinced it won’t happen in the near future.

Mark Durcan, CEO of Micron Technology, said in a 2014 interview that he expects it to be delayed indefinitely and didn’t see a reason for Micron to spend money on 18-inch research for at least the next five years. Dan Hutcheson, CEO of VLSI Research, doesn’t see 18-inch fabs going into production before 2020.

Other Resources About Semiconductors

Basic Wafer Terms & Definitions
Cutting Si Wafers Off-Axis
Oxygen Precipitation in Silicon
Properties of Glass as Related to Applications with Silicon
A Guide to SEMI Specifications for Si Wafers
Wet-Chemical Etching and Cleaning of Silicon


Silicon Wafer Die Count

Wafers are cut, or “diced,” into many pieces, each of which will become an IC. Manufacturers want to maximize the number of pieces, or dies, in each wafer to minimize the cost of making each die.

Wafers are round, but the constraints of dicing mean that the dies must have straight edges. Dies therefore have rectangular shapes and are usually square. Dies are often described by their aspect ratio, which is the ratio of a length of a die’s long side to the length of a short side. A square therefore has an aspect ratio of 1:1.

The difference in shapes of the wafer and dies makes calculating the maximum number of complete dies in a wafer a computationally complex problem. The wafer’s circular shape means that the dies at the edge of the wafer will be incomplete and therefore unusable.

Other factors that complicate this calculation include the dies’ aspect ratio, the space used by test structures, the alignment of the dies and the width of the scribe lines.

A simple comparison of the wafer’s surface area to the die’s surface area is easy to calculate with the following formula:

In the formula, DPW is dies-per-wafer, d is the wafer’s diameter and S is the die’s surface area. This formula divides the wafer’s surface area by the die’s surface area to provide the gross number of dies in a wafer.

However, this first-order approximation doesn’t consider losses due to incomplete dies, which become more significant as the die size increases. Higher order formulas use a correction factor to provide an acceptably accurate calculation of a wafer’s complete die count.

Several approaches to this problem exist, such as using a polynomial factor to scale the ratio of the wafer and die surface area. The following formula uses this method for square dice:

The following formula is more accurate for rectangular dies with a large aspect ratio:

Wafer Orientation

A silicon crystal has a diamond cubic structure, so the silicon atoms will be aligned in a particular direction when the crystal is sliced into wafers. The Miller index is commonly used describe the orientation of crystal lattices.

This index uses three integers to identify the family of planes to which a crystal belongs. The most orientations for silicon wafers are and , although is used much more often.

A wafer’s orientation is important because it affects many of its structural and electronic properties.

Each orientation provides distinct paths for transporting ions, so the depth of implanted ions is highly dependent on orientation. It’s also important in dicing since wafers are much easier to dice along their cleavage planes.

Orientation Notches

Wafers usually have one or more notches that provide information about the wafer. Wafers smaller than four inches use two notches at different angles to indicate the orientation of their crystallographic planes and the semiconductor type, especially for wafers. Wafers with a diameter of at least four inches have only one notch to indicate orientation.

Dopants For Silicon Wafers

Dopants are impurities that manufacturers intentionally add to the melt, typically for the purpose of controlling its electrical properties.

Doping generally increases the concentration of ion carriers, which increases the wafer’s electrical conductivity. A wafer is known as a degenerate semiconductor if its doping level is high enough to make it more of a conductor than a semiconductor. Degenerate semiconductors are often used as a replacement for metals in ICs.

A wafer’s doping concentration is typically indicated with a superscript on its semiconductor type, such that a negative symbol (-) is a lightly doped wafer and a positive symbol (+) is a highly doped wafer, often a degenerate semiconductor. Thus, p indicates lightly doped p-type semiconductor, while n+ indicates a highly doped n-type semiconductor.

The terms used to describe a wafer’s doping concentration are relative, since even the most highly doped wafer is still highly pure silicon. Doping concentrations are between 1013 and 1016 atoms of dopant per cubic centimeter (cm3), according to Technology of Integrated Circuits.

A silicon crystal contains 5×1022 atoms per cm3, so degenerate semiconductors are still more than 99.9999% silicon. Wafers may also contain some oxygen in the empty spaces of the silicon lattice.
While manufacturers minimize all unwanted contaminants in silicon wafers, they must be particularly concerned with metals. For example, Microelectronic Materials and Processes reports that the concentration of transition metals must be kept to a few parts per billion.

Everything You Need To Know About the Silicon Wafer Manufacturing Process

A silicon wafer, also known as a slice or substrate, is a thin slice of crystalline silicon. This semiconductor material is widely used in the manufacture of microelectronic devices such as integrated circuits (ICs) and solar cells.

A wafer serves as a substrate for these devices, allowing other components to be built in and on the wafer. The manufacture of silicon wafers includes many specific processes that can be categorized into the following four categories:

  • Silicon manufacturing
  • Photolithography
  • Oxidation
  • Diffusion and ion implantation

Virginia Semiconductor, Inc. is a leading manufacturer of prime silicon substrates. Production quantities of 1-150mm diameter silicon, and small quantities of custom-silicon substrates are also manufactured. Buy silicon wafers online.

Silicon Manufacturing

The manufacture of a silicon wafer begins with the purification of silicon, usually from quartz. This mineral is primarily composed of a crystalline form of silicon dioxide (SiO2), also known as silica. Silicon can also be purified on a commercial scale by heating a mixture of silica and carbon in an electric furnace.

ICs must contain only one type of crystal, making quality control extremely important during this manufacturing process. Semiconductor-grade silicon may only a few impurities per million parts of silicon.

Czochralski method

The Czochralski process is the most common method of growing single crystals of semiconducting materials, including silicon, germanium and gallium arsenide. It’s also used to make crystals of gemstones, metals and salts.

Pure silicon is placed in a crucible made from an inert material with a high melting point, usually quartz. The atmosphere must also be inert, so the chamber is typically filled with argon. The silicon is then heated to 1,425 degrees Celsius, which melts the silicon.

Other elements such boron or phosphorus may be added to the silicon at this stage to control the silicon’s electronic properties, a process known as doping the silicon. A seed crystal is mounted on a rod and oriented before dipping it into the molten silicon.

The crystal is then pulled out of the silicon while rotating it in a precise manner, which extracts a cylinder of monocrystalline silicon commonly known as an ingot. The length of an ingot is between one and two meters in length and will yield hundreds of wafers, each of which will be used to make thousands of ICs.

Wafer Manufacturing

Wafer manufacturing consists of four phases, including slicing, lapping, etching and polishing. The ingot is sliced into wafers with a diamond-tipped saw, which are sorted by thickness. The lapping phase involves removing wafers with damaged crystalline structures.

The remaining wafers are etched with a mild acidic solution to remove additional damage and polished to smooth the rough surfaces caused by the saw.

The unit crystal in a wafer contains 18 silicon atoms. These crystals have weak bonding along the cleavage planes, allowing the wafer to be easily split into four or six wedges. The planar orientation of each wedge is then classified according to the Miller index.


Photolithography is a technique that is used to create microscopic structures on a wafer. The phases of this process include photoresisting, photomasking and ashing.


The first step in photoresisting is to use chromium to create a pattern on a square glass plate. This plate is commonly known as a “photomask” or just “mask.” The wafer is then coated with a photoresist, which is a polymer that’s sensitive to ultraviolet light. A development process transfers the mask to the photoresist layer.

Underlying material can be removed from specific locations on the wafer by exposing those areas to ultraviolet (UV) light. UV light makes the photoresist more soluble in the developer, allowing the developer to wash away the photoresist.

The exposed silicon oxides, leaving an oxide layer in the areas exposed to UV light. The mask thus creates a desired pattern of silicon dioxide on the wafer.


The photomask is projected onto the wafer several times in a process known as stepping, Within the context of stepping, a photomask is usually referred to by the more specific term “photoreticle” or just “reticle.”

The reticle is carefully aligned with the wafer, and a high-intensity UV light exposes the photoresist through the reticle’s pattern. The specific exposure methods include contact, projection and proximity.

The pattern on the reticle is reduced each time it’s projected, so these projections are known as reduction reticles. A 5 times (5X) reduction reticle is the most common, but 2X, 4X and 10X reduction reticles are also used. ASM, Canon, GCA and Nikon manufacture steppers that use reduction reticles.


Ashing is a process that removes the photoresist from the wafer. This stage of photolithography involves spraying the wafer’s surface with a variety of organic solvents that dissolve the photoresist.

The most common technique uses oxygen plasma, usually in combination with a halogen gas such as fluorine, chlorine, bromine and iodine. This step is followed by cleaning with liquid solvents such as acids to remove any remaining residue.

This cycle typically must be repeated multiple times before the wafer is completely clean.


Oxidation is a key process step in manufacturing all silicon devices, although the optimum thickness depends on the specific application. Silicon dioxide is highly stable and easy to form, which is one of the reasons the silicon replaced germanium as the most common semiconductor.

A thin oxide layer has a thickness of about 10 nanomters (nm) and is typically used for metal-oxide-semiconductor (MOS) devices. Thick oxides have a thickness of about one micron and are used to isolate MOS devices from each other. Oxide layers may also be grown and subsequently removed to remove contaminants from the wafer’s surface.

Oxide Creation

The techniques for creating an oxide layer may be classified as growth or deposition.

The procedure for growing the oxide layer generally involves heating the water is an oxidizing atmosphere. Oxide growth techniques may be classified as dry oxidation or wet oxidation. The key variables in oxidation include temperature, reaction rate and the diffusion of oxide molecules through the substrate.

Contamination of the surface with metals can also adversely impact oxide quality by catalyzing undesired reactions.

Dry oxidation uses pure oxygen as the oxidizing atmosphere, which causes the oxide layer to grow very slowly. However, it also creates very uniform oxide layers with few defects at the silicon-oxide interface. The oxide produced by dry oxidation has a low surface-state charge, making it the best choice for MOS devices.

Wet oxidation uses water in the form of steam, which liberates hydrogen as a byproduct of oxidation. Hydrogen reacts with the oxide layer to produce imperfections on the wafer’s surface, which can degrade the device’s performance. Wet oxidation grows oxide layers more quickly and is more likely to be used for applications that require thick layers.

Oxide layers may also be deposited rather than grown. This process generally requires a reaction between a gaseous silicon compound and a gaseous oxidizer. Deposited oxides are typically used as an insulator between conductor layers in a wafer or as a protective overcoat. The large number of defect sites makes deposited oxides unsuitable for gate dielectrics in MOS transistors.

Oxide Removal

Etching is the process of removing unwanted oxide layers on the wafer and is classified into wet and dry techniques.

Wet etching involves dissolving oxides with a liquid chemical solution. These techniques are simpler and less expensive to perform than dry etching and are capable of high throughputs. However, they have adhesion problems and are unsuitable for etching features smaller than three microns.

One common wet etching technique uses hydrofluoric acid (HF), ammonium fluoride (NH4F) and water, where hydrofluoric acid is the etching agent and ammonium fluoride is a buffering agent that controls the acidity of the solution.

Dry etching uses gases in plasma form to remove oxides, which provides better control over line widths than wet etching. Dry etching may use a hard mask when the etch has a low selectivity for the photoresist or the photoresist would otherwise delaminate. The materials most commonly used to make a hard mask include silicon dioxide or silicon nitride (Si3N4).

Diffusion and Ion Implantation

The Czochralski method of growing silicon crystals may require dopants to be added to the molten silicon to control its electrical properties.

Photolithography is then used on the manufactured wafer to define circuit elements, which requires additional doping. The most common methods for performing this secondary stage of doping are diffusion and ion implantation.


Diffusion involves adding a liquid containing a dopant such as arsenic, boron or phosphorus to the wafer surface. The wafers are then spun at about 3,000 rpm for up to ten seconds to ensure that the dopant only adheres to the exposed areas on the wafer. The wafers are then heated to between 800 and 1,250 degrees Celsius to drive the dopant into the silicon.

Ion Implantation

Ion implantation uses a particle accelerator to drive the dopant into the silicon crystal to a depth of several microns. This damages the crystal, which must be repaired by slightly heating the wafer for a few minutes in a process known as annealing. The dopant used in ion implantation is typically created from a gas source, allowing the dopant purity to be very high.


Diffusion is a simpler technique than ion implantation, so its cost is lower. However, it’s an isotropic process, meaning that the dopants interact with each other to alter the diffusion rate. This phenomenon causes the dopants to be distributed less evenly.

Ion implantation doesn’t require heating the wafers to a high temperature, which can alter their shape. It also provides greater control over the concentration and distribution of the dopants. Ion implantation is an anisotropic process, so the dopant doesn’t spread as much as it does with diffusion.

This benefit makes self-aligned structures more accurate, thus improving the performance of MOS devices.

Thermal Oxidation For Silicon Wafers

Oxidation is an essential phase in the fabrication of silicon wafers that are used to make integrated circuits (ICs).

This process provides a number of benefits for bipolar and metal–oxide–semiconductor (MOS) transistors such as the electrical isolation between multilevel interconnected layers of an IC.

Oxidation also provides surface passivation, meaning it creates a barrier against corrosion. Additional benefits of oxidation include protecting ICs from the implantation of impurities in the substrate.

Applications For Oxidized Silicon Wafers

The process of oxidizing silicon wafers includes a variety of specific techniques that use heat to create a layer of silicon dioxide (SiO2) on top of the pure silicon that comprises the majority of the wafers.

Thermal oxidation is most useful for applications that require a low density of electrical charge at the interface between the silicon and SiO2 layers. ICs with multiple levels require vapor phase oxidation to create a SiO2 layer on top of the metal layer, although this process produces an oxide layer of lower quality than thermal oxidation.

Thermal oxidation techniques may generally be classified into dry and wet oxidation. The preferred method generally depends on the desired properties of the oxidation layer, especially its thickness. The purity of the oxide layer must also be very high to ensure the IC performs reliably.

Types Of Oxidation

Dry oxidation uses oxygen as shown by the chemical equation Si + O2 -> SiO2. A silicon atom directly reacts with an oxygen molecule to produce one molecule of silicon dioxide. This type of oxidation is best for thin oxide layers with a low charge at the interface. Dry oxidation is also the preferred process when contamination by sodium atoms is a concern.

Wet oxidation is based on the equation Si + 2H2O -> SiO2+2H2. Water in the form of steam reacts with silicon to produce silicon dioxide and hydrogen gas. This process is used to produce thick oxide layers with relatively low temperatures and high pressure.

The Thermal Oxidation Process For Silicon Wafers

  1. The thermal oxidation of silicon begins by placing the silicon wafers in a quartz rack, commonly known as a boat, which is heated in a quartz thermal oxidation furnace. The temperature in the furnace may be between 950 and 1,250 degrees Celsius under standard pressure. A control system is needed to keep the wafers within about 19 degrees Celsius of the desired temperature.
  2. Oxygen or steam is introduced into the thermal oxidation furnace, depending on the type of oxidation being performed.
  3. Oxygen from these gases then diffuses from the surface of the substrate through the oxide layer to the silicon layer. The composition and depth of the oxidation layer may be precisely controlled by parameters such as time, temperature, pressure and gas concentration.

A high temperature increases the oxidation rate, but it also increases the impurities and movement of the junction between the silicon and oxide layers.

These characteristics are particularly undesirable when the oxidation process requires multiple steps, as is the case with complex ICs. A lower temperature produces an oxide layer of higher quality, but also increases the growth time.

The typical solution to this problem is to heat the wafers at a relatively low temperature and high pressure to reduce the growth time.

An increase of one standard atmosphere (atm) decreases the required temperature by about 20 degrees Celsius, assuming all other factors are equal. Industrial applications of thermal oxidation use up to 25 atm of pressure with a temperature between 700 and 900 degrees Celsius.

The oxide growth rate is initially very fast but slows down as oxygen must diffuse through a thicker oxide layer to reach the silicon substrate. Almost 46 percent of the oxide layer penetrates the original substrate after oxidation is complete, leaving 54 percent of the oxide layer on top of the substrate.

Growth Rates With Different Types Of Oxidation

Wet oxidation has a higher growth rate than dry oxidation, all other factors being equal. The time needed to grow a layer of 0.1 microns (um) with wet oxidation is about 1.5 hours under typical conditions, while dry oxidation requires about 2.5 hours.

However, wet oxidation also produces oxides with more impurities. Dry oxidation is therefore the preferred approach for MOS ICs due to the very high oxide purity needed for reliable performance.

ICs that use very-large-scale-integration (VLSI) have oxide layers in the range of 2 to 20 nanometers (nm).

These thin oxide layers must be made with special techniques that use low temperature and pressure, resulting in a low growth rate. The typical temperature for this process is about 950 degrees Celsius with a pressure between 0.2 and 2 Torr, which is 1/760 of a standard atmosphere.

Thin oxide layers can also be grown with the use of hydrochloric acid (HCL) at an initial temperature of 1,000 degrees Celsius. Nitrous oxide (N2O) is then introduced and the temperature is increased to 1,250 degrees Celsius to precisely control the thickness.

Oxides with a thickness of up to 30 nm can be grown in less than 30 minutes with another technique that combines a temperature of 750 degrees Celsius with a pressure of 10 atm.

Masking For Dopants

SiO2 acts as a barrier, or mask, against the diffusion of dopant through the oxide layer. Dopants tend to accumulate near this layer, so precautions must be taken during oxidation to prevent this diffusion from occurring.

Dopant diffusion is slower through oxide than silicon, so the oxide thickness can be monitored to avoid inversion of a lightly-doped substrate. An oxide layer used for this purpose typically has a thickness between 0.5 and 0.7 um.

This masking property is only effective when the silicon is partially converted into SiO2. The optimum concentration and structure of SiO2 primarily depends on the dopant, which differs between semiconductor types.

The most common dopants for n-type semiconductors include antimony (Sb), arsenic (As) and phosphorus (P), while boron (B) is the most common dopant for p-type semiconductors.

Oxide Charges

Thermal oxidation imparts electrical charges on the oxide layer, whereas the silicon substrate should be electrically neutral.

These charges must be minimized because they change the characteristics of an IC. Electrical charges in a silicon wafer may be categorized into three types, consisting of a:

  1. fixed oxide charge (Qf),
  2. mobile ionic charge (Qm) and
  3. oxide trapped charge (Qt).

Qf is usually positive and can’t be charged or discharged. Its presence is only allowed within 3 nm of the Si-SiO2 interface. The density of Qf ranges from 10^10 to 10^12 per square centimeters (cm), depending on the oxidation and annealing conditions.

Qm is also positive in most cases. It’s usually caused by the ions of alkali elements such as sodium and potassium, although heavy metals and negative ions can also cause Qm. The typical density of Qm is between 10^10 and 10^12 square cm.

Qt may be positive or negative. It’s caused by defects in the oxide layer, typically electrons or holes. However, Qt may also be induced by other factors such as excessive current, ionizing radiation and avalanche injection in the oxide. The density of Qt ranges from 10^10 to 10^13 per square cm.

Stacking Faults

SiO2 is in a state of compression at the surface during thermal oxidation. This oxidative stress is due to the etchings that are made in the silicon before oxidation to produce a planar surface.

Etching produces a complex distribution of stress, which can deform the oxide layer. The stress is on the order of 7 x 10^9 dynes per square cm when the oxidation occurs at 950 degrees Celsius and drops to about 3 x 10^9 dynes per square cm at room temperature.

Thermal oxidation can also create stacking faults in the substrate, which are structural defects in the silicon lattice. These faults may be caused by mechanical damage to the surface that existed before oxidation and chemical contamination.

Stacking faults occur when excess silicon atoms accumulate at nucleation sites, resulting in the dislocation of silicon atoms in the lattice. Excess silicon atoms are most common near the Si–SiO2 interface, where some of these atoms can flow into the substrate. This process can increase the reverse current and degrade junction characteristics in MOS devices.

The formation of stacking faults is a function of several factors, including the specific contaminants, their level of electrical conductivity and the orientation of the substrate.

Orientation can also affect the growth rate of the oxide layer. For example, growth rate is greater in <100> substrates than in <111> substrates. These numbers in brackets indicate the substrate’s notation on the Miller Index, which describes the orientation of planes in a crystal lattice.

The length of stacking faults is generally a function of the oxidation temperature, such that a lower temperature results in shorter faults. Stacking faults don’t form at all below an oxidation temperature of 950 degrees Celsius.

The specific determination of stacking fault length is given by the equation dl/dt = k1[dx/dt]^n – k2 where:

  • dl/dt is the change in stacking fault length over time
  • k1 is a constant describing the growth mechanism and defect rate at the interface
  • dx/dt is the change in oxide thickness over time
  • n is the power dependence
  • k2 is a constant describing the retro-growth mechanism

Oxide Isolation Defects

Etching produces recessed oxides, resulting in stress along the edge of an oxidizing area. This stress can cause the isolated oxides to leak into nearby devices, so it must be relieved without damaging the substrate.

The most common solution is to use an oxidation temperature that’s high enough to create a viscous flow that reduces oxide isolation. Another approach is to create the oxide layer without etching the substrate. Some manufacturing processes also use a nitride mask to reduce the production of recessed oxides.