Thermal Oxidation For Silicon Wafers

Oxidation is an essential phase in the fabrication of silicon wafers that are used to make integrated circuits (ICs).

This process provides a number of benefits for bipolar and metal–oxide–semiconductor (MOS) transistors such as the electrical isolation between multilevel interconnected layers of an IC.

Oxidation also provides surface passivation, meaning it creates a barrier against corrosion. Additional benefits of oxidation include protecting ICs from the implantation of impurities in the substrate.

Applications For Oxidized Silicon Wafers

The process of oxidizing silicon wafers includes a variety of specific techniques that use heat to create a layer of silicon dioxide (SiO2) on top of the pure silicon that comprises the majority of the wafers.

Thermal oxidation is most useful for applications that require a low density of electrical charge at the interface between the silicon and SiO2 layers. ICs with multiple levels require vapor phase oxidation to create a SiO2 layer on top of the metal layer, although this process produces an oxide layer of lower quality than thermal oxidation.

Thermal oxidation techniques may generally be classified into dry and wet oxidation. The preferred method generally depends on the desired properties of the oxidation layer, especially its thickness. The purity of the oxide layer must also be very high to ensure the IC performs reliably.

Types Of Oxidation

Dry oxidation uses oxygen as shown by the chemical equation Si + O2 -> SiO2. A silicon atom directly reacts with an oxygen molecule to produce one molecule of silicon dioxide. This type of oxidation is best for thin oxide layers with a low charge at the interface. Dry oxidation is also the preferred process when contamination by sodium atoms is a concern.

Wet oxidation is based on the equation Si + 2H2O -> SiO2+2H2. Water in the form of steam reacts with silicon to produce silicon dioxide and hydrogen gas. This process is used to produce thick oxide layers with relatively low temperatures and high pressure.

The Thermal Oxidation Process For Silicon Wafers

  1. The thermal oxidation of silicon begins by placing the silicon wafers in a quartz rack, commonly known as a boat, which is heated in a quartz thermal oxidation furnace. The temperature in the furnace may be between 950 and 1,250 degrees Celsius under standard pressure. A control system is needed to keep the wafers within about 19 degrees Celsius of the desired temperature.
  2. Oxygen or steam is introduced into the thermal oxidation furnace, depending on the type of oxidation being performed.
  3. Oxygen from these gases then diffuses from the surface of the substrate through the oxide layer to the silicon layer. The composition and depth of the oxidation layer may be precisely controlled by parameters such as time, temperature, pressure and gas concentration.

A high temperature increases the oxidation rate, but it also increases the impurities and movement of the junction between the silicon and oxide layers.

These characteristics are particularly undesirable when the oxidation process requires multiple steps, as is the case with complex ICs. A lower temperature produces an oxide layer of higher quality, but also increases the growth time.

The typical solution to this problem is to heat the wafers at a relatively low temperature and high pressure to reduce the growth time.

An increase of one standard atmosphere (atm) decreases the required temperature by about 20 degrees Celsius, assuming all other factors are equal. Industrial applications of thermal oxidation use up to 25 atm of pressure with a temperature between 700 and 900 degrees Celsius.

The oxide growth rate is initially very fast but slows down as oxygen must diffuse through a thicker oxide layer to reach the silicon substrate. Almost 46 percent of the oxide layer penetrates the original substrate after oxidation is complete, leaving 54 percent of the oxide layer on top of the substrate.

Growth Rates With Different Types Of Oxidation

Wet oxidation has a higher growth rate than dry oxidation, all other factors being equal. The time needed to grow a layer of 0.1 microns (um) with wet oxidation is about 1.5 hours under typical conditions, while dry oxidation requires about 2.5 hours.

However, wet oxidation also produces oxides with more impurities. Dry oxidation is therefore the preferred approach for MOS ICs due to the very high oxide purity needed for reliable performance.

ICs that use very-large-scale-integration (VLSI) have oxide layers in the range of 2 to 20 nanometers (nm).

These thin oxide layers must be made with special techniques that use low temperature and pressure, resulting in a low growth rate. The typical temperature for this process is about 950 degrees Celsius with a pressure between 0.2 and 2 Torr, which is 1/760 of a standard atmosphere.

Thin oxide layers can also be grown with the use of hydrochloric acid (HCL) at an initial temperature of 1,000 degrees Celsius. Nitrous oxide (N2O) is then introduced and the temperature is increased to 1,250 degrees Celsius to precisely control the thickness.

Oxides with a thickness of up to 30 nm can be grown in less than 30 minutes with another technique that combines a temperature of 750 degrees Celsius with a pressure of 10 atm.

Masking For Dopants

SiO2 acts as a barrier, or mask, against the diffusion of dopant through the oxide layer. Dopants tend to accumulate near this layer, so precautions must be taken during oxidation to prevent this diffusion from occurring.

Dopant diffusion is slower through oxide than silicon, so the oxide thickness can be monitored to avoid inversion of a lightly-doped substrate. An oxide layer used for this purpose typically has a thickness between 0.5 and 0.7 um.

This masking property is only effective when the silicon is partially converted into SiO2. The optimum concentration and structure of SiO2 primarily depends on the dopant, which differs between semiconductor types.

The most common dopants for n-type semiconductors include antimony (Sb), arsenic (As) and phosphorus (P), while boron (B) is the most common dopant for p-type semiconductors.

Oxide Charges

Thermal oxidation imparts electrical charges on the oxide layer, whereas the silicon substrate should be electrically neutral.

These charges must be minimized because they change the characteristics of an IC. Electrical charges in a silicon wafer may be categorized into three types, consisting of a:

  1. fixed oxide charge (Qf),
  2. mobile ionic charge (Qm) and
  3. oxide trapped charge (Qt).

Qf is usually positive and can’t be charged or discharged. Its presence is only allowed within 3 nm of the Si-SiO2 interface. The density of Qf ranges from 10^10 to 10^12 per square centimeters (cm), depending on the oxidation and annealing conditions.

Qm is also positive in most cases. It’s usually caused by the ions of alkali elements such as sodium and potassium, although heavy metals and negative ions can also cause Qm. The typical density of Qm is between 10^10 and 10^12 square cm.

Qt may be positive or negative. It’s caused by defects in the oxide layer, typically electrons or holes. However, Qt may also be induced by other factors such as excessive current, ionizing radiation and avalanche injection in the oxide. The density of Qt ranges from 10^10 to 10^13 per square cm.

Stacking Faults

SiO2 is in a state of compression at the surface during thermal oxidation. This oxidative stress is due to the etchings that are made in the silicon before oxidation to produce a planar surface.

Etching produces a complex distribution of stress, which can deform the oxide layer. The stress is on the order of 7 x 10^9 dynes per square cm when the oxidation occurs at 950 degrees Celsius and drops to about 3 x 10^9 dynes per square cm at room temperature.

Thermal oxidation can also create stacking faults in the substrate, which are structural defects in the silicon lattice. These faults may be caused by mechanical damage to the surface that existed before oxidation and chemical contamination.

Stacking faults occur when excess silicon atoms accumulate at nucleation sites, resulting in the dislocation of silicon atoms in the lattice. Excess silicon atoms are most common near the Si–SiO2 interface, where some of these atoms can flow into the substrate. This process can increase the reverse current and degrade junction characteristics in MOS devices.

The formation of stacking faults is a function of several factors, including the specific contaminants, their level of electrical conductivity and the orientation of the substrate.

Orientation can also affect the growth rate of the oxide layer. For example, growth rate is greater in <100> substrates than in <111> substrates. These numbers in brackets indicate the substrate’s notation on the Miller Index, which describes the orientation of planes in a crystal lattice.

The length of stacking faults is generally a function of the oxidation temperature, such that a lower temperature results in shorter faults. Stacking faults don’t form at all below an oxidation temperature of 950 degrees Celsius.

The specific determination of stacking fault length is given by the equation dl/dt = k1[dx/dt]^n – k2 where:

  • dl/dt is the change in stacking fault length over time
  • k1 is a constant describing the growth mechanism and defect rate at the interface
  • dx/dt is the change in oxide thickness over time
  • n is the power dependence
  • k2 is a constant describing the retro-growth mechanism

Oxide Isolation Defects

Etching produces recessed oxides, resulting in stress along the edge of an oxidizing area. This stress can cause the isolated oxides to leak into nearby devices, so it must be relieved without damaging the substrate.

The most common solution is to use an oxidation temperature that’s high enough to create a viscous flow that reduces oxide isolation. Another approach is to create the oxide layer without etching the substrate. Some manufacturing processes also use a nitride mask to reduce the production of recessed oxides.

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