Everything You Need To Know About the Silicon Wafer Manufacturing Process

A silicon wafer, also known as a slice or substrate, is a thin slice of crystalline silicon. This semiconductor material is widely used in the manufacture of microelectronic devices such as integrated circuits (ICs) and solar cells.

A wafer serves as a substrate for these devices, allowing other components to be built in and on the wafer. The manufacture of silicon wafers includes many specific processes that can be categorized into the following four categories:

  • Silicon manufacturing
  • Photolithography
  • Oxidation
  • Diffusion and ion implantation

Virginia Semiconductor, Inc. is a leading manufacturer of prime silicon substrates. Production quantities of 1-150mm diameter silicon, and small quantities of custom-silicon substrates are also manufactured. Buy silicon wafers online.

Silicon Manufacturing

The manufacture of a silicon wafer begins with the purification of silicon, usually from quartz. This mineral is primarily composed of a crystalline form of silicon dioxide (SiO2), also known as silica. Silicon can also be purified on a commercial scale by heating a mixture of silica and carbon in an electric furnace.

ICs must contain only one type of crystal, making quality control extremely important during this manufacturing process. Semiconductor-grade silicon may only a few impurities per million parts of silicon.

Czochralski method

The Czochralski process is the most common method of growing single crystals of semiconducting materials, including silicon, germanium and gallium arsenide. It’s also used to make crystals of gemstones, metals and salts.

Pure silicon is placed in a crucible made from an inert material with a high melting point, usually quartz. The atmosphere must also be inert, so the chamber is typically filled with argon. The silicon is then heated to 1,425 degrees Celsius, which melts the silicon.

Other elements such boron or phosphorus may be added to the silicon at this stage to control the silicon’s electronic properties, a process known as doping the silicon. A seed crystal is mounted on a rod and oriented before dipping it into the molten silicon.

The crystal is then pulled out of the silicon while rotating it in a precise manner, which extracts a cylinder of monocrystalline silicon commonly known as an ingot. The length of an ingot is between one and two meters in length and will yield hundreds of wafers, each of which will be used to make thousands of ICs.

Wafer Manufacturing

Wafer manufacturing consists of four phases, including slicing, lapping, etching and polishing. The ingot is sliced into wafers with a diamond-tipped saw, which are sorted by thickness. The lapping phase involves removing wafers with damaged crystalline structures.

The remaining wafers are etched with a mild acidic solution to remove additional damage and polished to smooth the rough surfaces caused by the saw.

The unit crystal in a wafer contains 18 silicon atoms. These crystals have weak bonding along the cleavage planes, allowing the wafer to be easily split into four or six wedges. The planar orientation of each wedge is then classified according to the Miller index.


Photolithography is a technique that is used to create microscopic structures on a wafer. The phases of this process include photoresisting, photomasking and ashing.


The first step in photoresisting is to use chromium to create a pattern on a square glass plate. This plate is commonly known as a “photomask” or just “mask.” The wafer is then coated with a photoresist, which is a polymer that’s sensitive to ultraviolet light. A development process transfers the mask to the photoresist layer.

Underlying material can be removed from specific locations on the wafer by exposing those areas to ultraviolet (UV) light. UV light makes the photoresist more soluble in the developer, allowing the developer to wash away the photoresist.

The exposed silicon oxides, leaving an oxide layer in the areas exposed to UV light. The mask thus creates a desired pattern of silicon dioxide on the wafer.


The photomask is projected onto the wafer several times in a process known as stepping, Within the context of stepping, a photomask is usually referred to by the more specific term “photoreticle” or just “reticle.”

The reticle is carefully aligned with the wafer, and a high-intensity UV light exposes the photoresist through the reticle’s pattern. The specific exposure methods include contact, projection and proximity.

The pattern on the reticle is reduced each time it’s projected, so these projections are known as reduction reticles. A 5 times (5X) reduction reticle is the most common, but 2X, 4X and 10X reduction reticles are also used. ASM, Canon, GCA and Nikon manufacture steppers that use reduction reticles.


Ashing is a process that removes the photoresist from the wafer. This stage of photolithography involves spraying the wafer’s surface with a variety of organic solvents that dissolve the photoresist.

The most common technique uses oxygen plasma, usually in combination with a halogen gas such as fluorine, chlorine, bromine and iodine. This step is followed by cleaning with liquid solvents such as acids to remove any remaining residue.

This cycle typically must be repeated multiple times before the wafer is completely clean.


Oxidation is a key process step in manufacturing all silicon devices, although the optimum thickness depends on the specific application. Silicon dioxide is highly stable and easy to form, which is one of the reasons the silicon replaced germanium as the most common semiconductor.

A thin oxide layer has a thickness of about 10 nanomters (nm) and is typically used for metal-oxide-semiconductor (MOS) devices. Thick oxides have a thickness of about one micron and are used to isolate MOS devices from each other. Oxide layers may also be grown and subsequently removed to remove contaminants from the wafer’s surface.

Oxide Creation

The techniques for creating an oxide layer may be classified as growth or deposition.

The procedure for growing the oxide layer generally involves heating the water is an oxidizing atmosphere. Oxide growth techniques may be classified as dry oxidation or wet oxidation. The key variables in oxidation include temperature, reaction rate and the diffusion of oxide molecules through the substrate.

Contamination of the surface with metals can also adversely impact oxide quality by catalyzing undesired reactions.

Dry oxidation uses pure oxygen as the oxidizing atmosphere, which causes the oxide layer to grow very slowly. However, it also creates very uniform oxide layers with few defects at the silicon-oxide interface. The oxide produced by dry oxidation has a low surface-state charge, making it the best choice for MOS devices.

Wet oxidation uses water in the form of steam, which liberates hydrogen as a byproduct of oxidation. Hydrogen reacts with the oxide layer to produce imperfections on the wafer’s surface, which can degrade the device’s performance. Wet oxidation grows oxide layers more quickly and is more likely to be used for applications that require thick layers.

Oxide layers may also be deposited rather than grown. This process generally requires a reaction between a gaseous silicon compound and a gaseous oxidizer. Deposited oxides are typically used as an insulator between conductor layers in a wafer or as a protective overcoat. The large number of defect sites makes deposited oxides unsuitable for gate dielectrics in MOS transistors.

Oxide Removal

Etching is the process of removing unwanted oxide layers on the wafer and is classified into wet and dry techniques.

Wet etching involves dissolving oxides with a liquid chemical solution. These techniques are simpler and less expensive to perform than dry etching and are capable of high throughputs. However, they have adhesion problems and are unsuitable for etching features smaller than three microns.

One common wet etching technique uses hydrofluoric acid (HF), ammonium fluoride (NH4F) and water, where hydrofluoric acid is the etching agent and ammonium fluoride is a buffering agent that controls the acidity of the solution.

Dry etching uses gases in plasma form to remove oxides, which provides better control over line widths than wet etching. Dry etching may use a hard mask when the etch has a low selectivity for the photoresist or the photoresist would otherwise delaminate. The materials most commonly used to make a hard mask include silicon dioxide or silicon nitride (Si3N4).

Diffusion and Ion Implantation

The Czochralski method of growing silicon crystals may require dopants to be added to the molten silicon to control its electrical properties.

Photolithography is then used on the manufactured wafer to define circuit elements, which requires additional doping. The most common methods for performing this secondary stage of doping are diffusion and ion implantation.


Diffusion involves adding a liquid containing a dopant such as arsenic, boron or phosphorus to the wafer surface. The wafers are then spun at about 3,000 rpm for up to ten seconds to ensure that the dopant only adheres to the exposed areas on the wafer. The wafers are then heated to between 800 and 1,250 degrees Celsius to drive the dopant into the silicon.

Ion Implantation

Ion implantation uses a particle accelerator to drive the dopant into the silicon crystal to a depth of several microns. This damages the crystal, which must be repaired by slightly heating the wafer for a few minutes in a process known as annealing. The dopant used in ion implantation is typically created from a gas source, allowing the dopant purity to be very high.


Diffusion is a simpler technique than ion implantation, so its cost is lower. However, it’s an isotropic process, meaning that the dopants interact with each other to alter the diffusion rate. This phenomenon causes the dopants to be distributed less evenly.

Ion implantation doesn’t require heating the wafers to a high temperature, which can alter their shape. It also provides greater control over the concentration and distribution of the dopants. Ion implantation is an anisotropic process, so the dopant doesn’t spread as much as it does with diffusion.

This benefit makes self-aligned structures more accurate, thus improving the performance of MOS devices.


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