Silicon Wafer Properties Explained

A silicon wafer, also known as a slice or substrate, is a thin slice of crystalline silicon. It’s primarily used as the substrate for integrated circuits (ICs) since silicon is a highly stable semiconductor.

The crystal used to make wafers must be more than 99.9999999% pure silicon, which presents significantly technical challenges in their manufacture.

The Czochralski process is the most common method for growing highly pure crystals made of semiconductors such as silicon and germanium: The silicon is melted under sterile conditions, and other elements known as dopants are often added to the molten silicon, or melt.

A seed crystal is then pulled from the melt and formed into a cylindrical ingot known as a boule, according to Microelectronic Materials and Processes. After the boule cools, it’s sliced into wafers with a wire saw, commonly known as a wafer saw. The wafers are cleaned with a series of weak acids to remove contaminants and repair damage caused by the wafer saw.

A particular application requires a wafer to have very specific properties. Buyers must therefore consider a variety of properties when selecting a batch of silicon wafers, including the following:

  • Size
  • Die count
  • Orientation
  • Dopants

Silicon Wafer Size

The number of chips that a wafer can produce is proportional to its surface area, but its fabrication cost increases more slowly than the surface area. The wafer industry therefore has a strong financial incentive to make the largest wafers that are commercially practical, especially considering the small size and high value of ICs.

Wafer size has continued to increase, with a diameter of 300 millimeters (mm) being the current maximum. The transition from 200mm to 300mm wafers on a commercial scale began in 2000, and reduced the cost per die by 30 to 40 percent.

However, this change required the wafer industry to overcome significant technical challenges and a large investment in new infrastructure.


We have also published a list of common silicon wafer terms and definitions if you need more background on some of the language used in this article.


Diameter Of Silicon Wafers

Wafers are round, with diameters ranging from 25mm to 300mm. F450C reports that the following sizes are currently available:

  • 25mm
  • 51mm
  • 76mm
  • 100mm
  • 130mm
  • 150mm
  • 200mm
  • 300mm
  • 450mm

Wafers are commonly known by their diameter to the nearest inch, even though they’re measured in millimeters.

For example, a wafer with a diameter of 300 mm is known as a “12-inch wafer,” although its actual diameter is only about 11.8 inches.

Likewise, a semiconductor fabrication plant, or fab, is also known by the diameter of its wafers to the nearest inch. A fab that makes 300-mm wafers is therefore known as a “12-inch plant.”

Wafer Thickness

A larger wafer must be thicker, since it must support its own weight without cracking during handling. However, the increase in thickness is significantly less than the increase in diameter.

For example, a one-inch wafer is typically about 250 microns (µm) thick, while the thickness of a 12-inch wafer is about 775 µm. Despite being almost 12 times wider than the one-inch wafer, a 12-inch wafer is only slightly more than three times thicker.

Transition to 18-Inch Wafers

The next size for wafers is expected to be 450mm, or about 18 inches, although considerable debate currently exists as to if and when this change might occur.

EE Times reported in 2008 that Intel, TSMC and Samsung were each conducting independent research on making their own prototypes for an 18-inch wafer. However, no manufacturer has yet produced a commercially viable wafer of this size as of 2017.

Lithographer Chris Mack stated in a 2012 interview published in Semiconductor Engineering that 450mm wafers would only reduce the cost per die of 300mm wafers by 10 to 20 percent.

Mack argues that the primary reason for such a modest decrease is that the majority of wafer processing costs are due to lithography rather than the manufacture of the wafer itself.

Lithography doesn’t provide the scalability that increasing wafer size does because lithography costs are related to surface area more than wafer count.

Increasing the diameter size improves a fab’s throughput, which ultimately reduces the cost of the ICs made from those wafers. Despite the productivity improvement, semiconductor manufacturers have significant concerns about receiving an adequate return on their investment in new fabrication equipment.

The change from 8-inch to 12-inch wafers required a major investment that had to be made during the economic downturn caused by the dot-com bubble burst in 2000.

While 8-inch fabs only need to be partially automated, 12-inch fabs must be fully automated. An 18-inch fab will require similar retooling, meaning only some of the existing equipment can be used for the new wafer size.

Furthermore, larger wafers incur additional processing costs. The ingots for 18-inch wafers will weigh 3X more than the ingots for 12-inch wafers, so they’ll need to spend 3X longer cooling on the ramp.

The timeline for the transition to 18 inches is currently uncertain, but many industry experts are convinced it won’t happen in the near future.

Mark Durcan, CEO of Micron Technology, said in a 2014 interview that he expects it to be delayed indefinitely and didn’t see a reason for Micron to spend money on 18-inch research for at least the next five years. Dan Hutcheson, CEO of VLSI Research, doesn’t see 18-inch fabs going into production before 2020.


Other Resources About Semiconductors

Basic Wafer Terms & Definitions
Cutting Si Wafers Off-Axis
Oxygen Precipitation in Silicon
Properties of Glass as Related to Applications with Silicon
A Guide to SEMI Specifications for Si Wafers
Wet-Chemical Etching and Cleaning of Silicon


 

Silicon Wafer Die Count

Wafers are cut, or “diced,” into many pieces, each of which will become an IC. Manufacturers want to maximize the number of pieces, or dies, in each wafer to minimize the cost of making each die.

Wafers are round, but the constraints of dicing mean that the dies must have straight edges. Dies therefore have rectangular shapes and are usually square. Dies are often described by their aspect ratio, which is the ratio of a length of a die’s long side to the length of a short side. A square therefore has an aspect ratio of 1:1.

The difference in shapes of the wafer and dies makes calculating the maximum number of complete dies in a wafer a computationally complex problem. The wafer’s circular shape means that the dies at the edge of the wafer will be incomplete and therefore unusable.

Other factors that complicate this calculation include the dies’ aspect ratio, the space used by test structures, the alignment of the dies and the width of the scribe lines.

A simple comparison of the wafer’s surface area to the die’s surface area is easy to calculate with the following formula:

In the formula, DPW is dies-per-wafer, d is the wafer’s diameter and S is the die’s surface area. This formula divides the wafer’s surface area by the die’s surface area to provide the gross number of dies in a wafer.

However, this first-order approximation doesn’t consider losses due to incomplete dies, which become more significant as the die size increases. Higher order formulas use a correction factor to provide an acceptably accurate calculation of a wafer’s complete die count.

Several approaches to this problem exist, such as using a polynomial factor to scale the ratio of the wafer and die surface area. The following formula uses this method for square dice:

The following formula is more accurate for rectangular dies with a large aspect ratio:

Wafer Orientation

A silicon crystal has a diamond cubic structure, so the silicon atoms will be aligned in a particular direction when the crystal is sliced into wafers. The Miller index is commonly used describe the orientation of crystal lattices.

This index uses three integers to identify the family of planes to which a crystal belongs. The most orientations for silicon wafers are and , although is used much more often.

A wafer’s orientation is important because it affects many of its structural and electronic properties.

Each orientation provides distinct paths for transporting ions, so the depth of implanted ions is highly dependent on orientation. It’s also important in dicing since wafers are much easier to dice along their cleavage planes.

Orientation Notches

Wafers usually have one or more notches that provide information about the wafer. Wafers smaller than four inches use two notches at different angles to indicate the orientation of their crystallographic planes and the semiconductor type, especially for wafers. Wafers with a diameter of at least four inches have only one notch to indicate orientation.

Dopants For Silicon Wafers

Dopants are impurities that manufacturers intentionally add to the melt, typically for the purpose of controlling its electrical properties.

Doping generally increases the concentration of ion carriers, which increases the wafer’s electrical conductivity. A wafer is known as a degenerate semiconductor if its doping level is high enough to make it more of a conductor than a semiconductor. Degenerate semiconductors are often used as a replacement for metals in ICs.

A wafer’s doping concentration is typically indicated with a superscript on its semiconductor type, such that a negative symbol (-) is a lightly doped wafer and a positive symbol (+) is a highly doped wafer, often a degenerate semiconductor. Thus, p indicates lightly doped p-type semiconductor, while n+ indicates a highly doped n-type semiconductor.

The terms used to describe a wafer’s doping concentration are relative, since even the most highly doped wafer is still highly pure silicon. Doping concentrations are between 1013 and 1016 atoms of dopant per cubic centimeter (cm3), according to Technology of Integrated Circuits.

A silicon crystal contains 5×1022 atoms per cm3, so degenerate semiconductors are still more than 99.9999% silicon. Wafers may also contain some oxygen in the empty spaces of the silicon lattice.
While manufacturers minimize all unwanted contaminants in silicon wafers, they must be particularly concerned with metals. For example, Microelectronic Materials and Processes reports that the concentration of transition metals must be kept to a few parts per billion.

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