Silicon On Insulator – SOI Wafers: The Basics

Silicon on insulator (SOI) technology is the use of an insulating layer between the silicon substrate and an upper layer of silicon in silicon wafers. Its primary purpose is to improve performance over conventional silicon substrates by reducing electrical losses.

The insulator is usually silicon dioxide or sapphire, which is primarily aluminum oxide with metal impurities. SOI wafers that use sapphire as the insulator may be known more specifically as silicon on sapphire (SOS).

The best insulator in an SOI wafer depends on the intended application, with silicon dioxide being most common in microelectronics due to its ability to reduce short-channel effects.

Sapphire is used more often in radiation-sensitive applications such as high-performance radio frequency (RF) applications. The ideal thickness of the insulating and upper silicon layers in SOI wafers also vary according to application.

How are SOI wafers manufactured?

SOI substrates are generally compatible with conventional fabrication processes, so an SOI process can be implemented without purchasing additional equipment or significantly retooling an existing factory.

The most significant challenges in SOI manufacture include maintaining the thickness of the buried oxide (BOX) layer within a very narrow range and preventing the differential stress in the upper silicon layer from exceeding design limitations.

The transistor’s threshold voltage is also a critical concern in SOI design, since it depends on factors such as the voltage applied to the device and its operational history.

The primary barrier to adoption of SOI devices has historically been the increase of substrate costs, according to IBM. Silicon dioxide-based SOI wafers can be manufactured with several distinct techniques, including Separation by Implantation of Oxygen (SIMOX), wafer bonding and seed methods.

Wafer bonding

Wafer bonding is a packaging technology for microelectronics and similar devices, including microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS) and optoelectronics.

It bonds the silicon dioxide layer directly to the upper silicon layer, most of which is later removed. Various specific wafer-bonding techniques are currently used, including the Smart Cut method used by Soitec.

This method uses ion implantation to create the silicon dioxide layer under the wafer’s surface and exfoliation to control the thickness of the upper silicon layer. Silicon Genesis Corporation uses a technology called NanoCleave that stresses the interface between a silicon layer and a layer of silicon-germanium alloy to separate the silicon layer.

A wafer bond is intended to create a mechanically stable hermetic seal over the wafer that protects it from water vapor and foreign objects. These bonds must therefore be evaluated according to their strength and hermeticity, which may be destructive or nondestructive.

Destructive techniques require sampling and typically involve tensile or shear testing. Other forms of destructive testing include subjecting the wafers to a carefully chosen atmosphere and pressure. Nondestructive testing usually consists of using optical methods to inspect the wafers for cracks or interfacial voids.

The diameter of a bonded wafer typically ranges from about 50 millimeters (mm) to 150mm. The thickness of the wafer is between 10 microns (µm) and 2,000 µm, with a tolerance between 1 and 25 µm.

The thickness of the silicon dioxide layer ranges from 0.5 to 4 µm, and the thickness of the wafer handle is between 100 µm and 2,000 µm. The electrical resistivity of the wafer and handle is between 0.00055 and 10,000 ohm-cm. Bonded wafers may have any crystal orientation and use any dopant.


SIMOX (Separation by Implantation of Oxygen) uses ion implantation to add oxygen ions into the substrate, according to U.S. Patent 5,061,642 and U.S. Patent 5,888,297.

Ion implantation involves accelerating ions into a solid target at low temperature, which alters the chemical and physical properties of the target. In the case of wafer fabrication, the oxygen ions combine with the silicon atoms in the substrate to form silicon dioxide. The concentration of oxygen ions determines the electrical conductivity of the substrate.

The SIMOX follows ion implantation with annealing at high temperature. Annealing involves heating the substrate to slightly above silicon’s recrystallization temperature for a specific period of time and allowing it to cool in a controlled manner. This process creates a layer of silicon dioxide under the substrate’s surface, which is the insulating layer of the SIO structure.

Seed methods

U.S. Patent 5,417,180 describes a seed method of producing SOI wafers, which generally involves growing the upper silicon layer directly onto the insulator.

Seed methods require a template to ensure the silicon is deposited onto the insulator evenly, a process scientifically as homoepitaxy. Techniques for achieving homoepitaxy include using an insulator with the appropriate crystalline orientation and treating the insulator chemically.

SOI device types

An SOI metal–oxide–semiconductor field-effect transistor (MOSFET) has a semiconductor layer on top of an insulator layer. U.S Patent 6,835,633 describes a structure that uses silicon as the semiconductor and a BOX inside a semiconductor layer as the insulator.

SOI MOSFET devices are primarily used by the computer industry, especially in static random access memory (SRAM) chips. SOI MOSFET devices may be classified into fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) types.

FDSOI MOSFETs use a very thin p-type film between the gate oxide (GOX) and BOX, so the depleted region covers the entire film. The GOX is less depleted than the rest of the MOSFET, which increases switching speed due to the increase in inversion charges.

PDSOI devices use a thicker film between the GOX and BOX, which prevents the depleted region from covering the whole film. This characteristic causes PDSOI MOSFETs to behave more like bulk MOSFETS than FDSOI MOSFETs.

The BOX’s depletion charge suppresses the capacitance of the depleted region, substantially reducing the subthreshold swing. This effect lowers a FDSOI MOSFETs gate bias, which reduces its power requirements. Numerical simulations show the minimum theoretical subthreshold swing of these devices to be 60 millivolts (mV) per decade, which MOSFETs can currently achieve.

The BOX in a FDSOI MOSFET prevents the source and drain electric fields from interfering with each other, which provide other advantages over bulk MOSFETs such as reduced threshold voltage roll off. However, the fact that the film isn’t connected to any of the MOSFET’s supplies creates a floating body effect (FBE).

This phenomenon means that the MOSFET’s body forms a capacitor against the insulating layer, causing an accumulated charge that can create adverse effects such as off-state current leakage.

Benefits of applying SOI technology

SOI technology is one of many strategies that wafer manufacturers are using to continue the miniaturization of microelectronic devices. This trend is embodied in Moore’s Law, which holds that the number of transistors in an integrated circuit (IC) doubles about every two years.

The specific benefits of SOI technology over conventional silicon include a lower parasitic capacitance due to the upper silicon’s insulation from the bulk silicon substrate, which reduces power consumption.

Parasitic capacitance, also known as stray capacitance, is a capacitance that occurs between the parts of an electronic component due to their close proximity. It’s generally undesirable, as it causes circuit elements to deviate from their ideal electrical behavior.

The isolation of the upper silicon layer from the substrate in an SOI wafer increases its resistance to latchup, which is a type of low-impedance short circuit. Latchup occurs between a MOSFET’s power supply rails, resulting in a disruption of power or even damage to the MOSFET. It also requires a power cycle to correct.

SOI wafers have greater resistance to radiation, making them less prone to soft errors. The insulating layer also reduces current leakage, which increases their power efficiency.

The higher density also increases the yield, thus improving wafer utilization. Additional advantages of SOI wafers include a reduced dependency on temperature and fewer antenna issues.

Applications for SOI wafers

The applications for SOI wafers include microelectronics, radio frequency (RF) and photonics.


The most common use of SOI wafers is in electronics. The first example of this application occurred in 2000, when IBM implemented SOI in its RS64-IV PowerPC-AS microprocessor, commonly known as “Istar.” AMD has made regular use of SOI technology in its processors since 2001, including its 32nm, 45nm, 65nm, 90nm and 130nm processors.

These processors are available in single, dual, quad, six and eight cores. Freescale also adopted SOI technology for its PowerPC 7455 CPU in 2001, and its current SOI products include its 45nm, 90nm, 130nm and 180nm CPUs.

SOI is also becoming popular in video game consoles, especially those using the 90nm Power Architecture processors. These CPUs are used in a range of consoles, including Microsoft’s Xbox 360, Sony’s Playstation 3 and Nintendo’s Wii. Researchers at Intel built a silicon rib waveguide Raman laser in 2005 that used a single SOI CPU.

However, Intel’s commercial CPUs continue use conventional complementary metal–oxide–semiconductor (CMOS) technology by improving performance through advancements such as High-K Metal Gate (HKMG) and Tri-gate transistors.

RF Applications

Peregrine Semiconductor began developing SOI technology for high-performance RF applications in 1990, and its patented SOS process is now widely used. This device essentially consists of a conventional 0.5 μm CMOS with a sapphire substrate.

The primary benefits of an insulating sapphire substrate in RF applications include improved isolation and tolerance for electrostatic discharge (ESD). Other companies also use SOI technology for RF applications such as cellular radios and smartphones.


Silicon Photonics: An Introduction by Graham T. Reed and Andrew P. Knights describes the wide use of SOI wafers in photonics, which is the study of the generation, detection and manipulation of light.

These wafers are used in optical devices such as waveguides such that the insulating layer allows infrared light from internal reflection to propagate through the silicon layer. The surface of the waveguide is often left uncovered, allowing this infrared light to be detected by a sensor. It may also be covered, usually with a silica cladding.
For more information on SOI wafers or other silicon wafer products, contact us online or call us at 540-373-2900.

Other Resources About Semiconductors

Basic Wafer Terms & Definitions
Cutting Si Wafers Off-Axis
Oxygen Precipitation in Silicon
Properties of Glass as Related to Applications with Silicon
A Guide to SEMI Specifications for Si Wafers
Wet-Chemical Etching and Cleaning of Silicon


Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s