How Much Does A Silicon Wafer Cost

A silicon wafer is a thin slice of crystalline silicon, which serves as a substrate for microelectronic devices. It’s most commonly used in the manufacture of integrated circuits (ICs), but wafers are also used to make solar cells.

The fabrication process of a silicon wafer involves many complex steps, including the formation of the crystal, deposition of various materials and photolithographic patterning. The completed microcircuits must also be separated and packaged for sale.

Wafers must be of extremely high quality for an IC to perform effectively, which is the primary factor for their cost. The following steps have the greatest effect on the cost of a silicon wafer:

  • Size
  • Growth method
  • Doping
  • Planar orientation

Size Of Silicon Wafers

Silicon wafers are round, with diameters ranging from 25.4 millimeters (mm) to 300 mm, according to The Facilities 450mm Consortium. The exact measurements of the wafers are in millimeters, although they’re commonly referred to by their closest measurement in inches.

For example, a wafer with a diameter of 25.4 mm across is almost exactly one inch across and is referred to as a “one-inch” wafer. A 300-mm wafer has a diameter of about 11.8 inches and is known as a “12-inch” wafer. Fabrication plants, or fabs, are known by the size of the wafers they produce, as in a “12-inch fab.”

The manufacture of larger wafers has greater throughput, which reduces its cost per die. The silicon wafer industry is therefore strongly motivated to increase the size of its wafers.

The 12-inch wafer is currently state of the art, which replaced the 8-inch wafer as the largest commercially available size beginning in 2000. This transition reduced the cost per die of wafers by 30-40 percent. Companies such as Intel, Samsung and TSMC are currently researching methods of manufacturing an 18-inch wafer, although this size still presents significant technical challenges.

Silicon wafers also become thicker as their surface area increases since they must support their own weight during handling without cracking. The thickness of a wafer ranges from a minimum of 250 microns (µm) for a one-inch wafer to 775 µm for a 12-inch wafer. The increased thickness also contributes to the increased cost of larger wafers.

The Impact Of Die Counts On Silicon Wafer Costs

Manufacturers need to maximize the number of complete dies that a wafer can make to minimize the cost per die.

This goal presents a complex computational problem, since wafers are round and dies are rectangular. This difference in shape results in a number of incomplete dies at the edge of the wafer, which can’t be sold as a functional part.

The maximum die count of a wafer depends on factors such as the aspect ratio of the dies, the width of the scribe lines separating the dies and the space required by test structures.

Formulas for estimating the gross die per wafer (DPW) can account for the wafer area lost to incomplete dies, but not the additional losses resulting from defects and parametric problems.

The formula DPW=[πd^2/(4S)] provides a first-order approximation of the number of dies that a wafer will produce, where DPW is the number of wafers, d is the wafer diameter and S is the width of the dies. This formula simply provides the ratio of the wafer’s surface area to the die’s surface area, so it doesn’t account for incomplete dies.

Higher order approximations like the following use a correction factor to estimate the number of complete dies that a wafer will actually produce:

How Size Impacts Wafer Costs

The total cost of making a wafer increases with its size, although its cost per unit surface area decreases. This relationship means that larger wafers reduce the price of the dies.

The retail price of a basic one-inch silicon wafer without any special features is about $21 when purchased in quantity. A bulk purchase of similar 6-inch silicon wafers costs about $125 per unit, which is about 6 times the price of the one-inch wafer.

However, the surface area of the six-inch wafer is about 36 times greater than that of the one-inch wafer. The cost of dies made from the six-inch wafers will therefore be one sixth that of dies made from the one-inch wafer, all other factors being equal. This result clearly illustrates the financial incentive for increasing wafer sizes.

Growth Method For Silicon Wafers

Wafers are composed of virtually pure crystalline silicon. The commercial processes for forming crystalline silicon include the Czochralski process and the float-zone method, although the Czochralski process is much more common.

Czochralski Process

Microelectronic Materials and Processes reports that the Czochralski process involves pulling a seed crystal from the molten silicon, or “melt,” to form a cylindrical ingot of crystalline silicon known as a boule.

Highly pure silicon is melted in a crucible at about 1,425 degrees Celsius, which is just about silicon’s melting point of 1,414 degrees Celsius.

This process requires an inert environment to prevent chemical reactions in the melt, so the Czochralski process is typically performed in an atmosphere composed inert gas such as silicon. The crucible must also be made of an inert material such as quartz, which is highly stable.

A seed crystal is mounted on a rod and precisely oriented before dipping it into the melt. The rod is then pulled up and rotated simultaneously to extract an ingot from the melt.

The Czochralski process requires a high degree of control over factors such as temperature, pulling speed and rotation speed to avoid instabilities in the ingot during the growth process.

Float Zone Process

The float zone process, also known as vertical zone melting, uses a vertical configuration of silicon that has enough surface tension to prevent the charge from melting. A rod of extremely pure crystalline silicon is passed through a radio-frequency (RF) heating coil to create a small area of molten silicon.

A seed crystal is placed at one end of this zone. The molten zone carries impurities away since most impurities are more soluble in molten silicon than crystalline silicon. This process is carried out in an inert environment like the Czochralski process.

The float zone method eliminates the need for a containment vessel, which is a common source of contamination. The silicon obtained with this method therefore has a lower concentration of impurities than that yielded by the Czochralski process, especially light contaminants such as carbon and oxygen.

Nitrogen is a light impurity that’s now intentionally introduced to float zone silicon for the purpose of controlling micro-defects and increase its mechanical strength.

The primary disadvantage of the float zone method is that it can’t produce wafers larger than six inches due to limitations imposed by the silicon’s surface tension. This method is therefore less commercially useful than the Czochralski process, despite the greater purity of the silicon.

How Growth Method Impacts Wafer Costs

The float zone method is only used for specific applications where a higher purity requirement offsets the limitations on wafer size. The limited use of float zone silicon significantly increases the cost of wafers made with this method.

For example, a basic 6-inch wafer made with the float zone method costs about $60 when purchased in bulk. In comparison, a bulk purchase of similar wafers made with the Czochralski process costs about $29.

Silicon Wafer Doping

Additional elements can be added to the molten silicon in precise quantities to control the electrical properties of a silicon wafer.

Phosphorus is the most common dopant used to make n-type semiconductors, while boron is typically used for p-type semiconductors. Arsenic and antimony are also used to dope silicon wafers.

The concentration of dopant is typically between 10^13 and 10^16 atoms per cubic centimeter of silicon, according to Technology of Integrated Circuit. A cubic centimeter of crystallized silicon contains about 5×10^22 atoms, so a doped silicon wafer is still more than 99.9999% pure.

Oxygen may also be added to the melt to occupy spaces outside the regular crystal lattices, which strengthens the crystal.

While the impurities in a wafer must be kept low in general, metal impurities are of particular concern since they conduct electricity. For example, the concentration of transition metals must be kept below a few parts per billion.

The Impact Of Doping On Wafer Costs

The effect of dopants on the price of a silicon wafer is quite small, compared with other factors. An undoped four-inch wafer with a thickness of about 500 µm has a unit cost of $29 for bulk purchases.

The same wafer costs about $32 when doped with boron. A wafer that’s doped with phosphorus actually costs less, with a unit cost of $27.

Planar Orientation Of Silicon Wafers

The lattice of crystalline silicon may be aligned in several ways when it’s sliced into wafers. These crystal orientations are described by the Miller index, which uses three integers to determine the crystal’s family of lattice planes. The orientations and are the most common for silicon wafers, according to Handbook of Semiconductor Silicon Technology.

Planar orientation is important in wafers because a crystal’s electrical and structural properties are highly anisotropic, meaning they’re dependent upon orientation.

This is particularly true of ion implantation depths, since each planar direction provides distinct paths for transplanting ions.

Orientation is also a critical factor for cutting, or dicing, the wafer. The wafer must be scored along a cleavage plane, so it can be diced into individual dies.

The Impact Of Planar Orientation On Price

Undoped wafers usually have an orientation of , while wafers with an orientation of are primarily used for doping. Doped wafers with an orientation of often cost slightly less, all other factors being equal.

For example, a four-inch wafer with a thickness of 500 µm and a resistivity of 0.0006 ohm-meters costs about $45, while a similar wafer costs only $40.

Have More Silicon Wafer Cost Questions?

Virginia Semiconductor is a fully integrated silicon wafer manufacturer. We have been making wafers from scratch since 1997, allowing us to easily repeat specifications from batch to batch. For 20 years, we have been the world’s number one online source for silicon wafers and substrates.

If you have any additional questions about costs or other silicon wafer related inquiries, contact us online here or call us at 540.373.2900.


Other Resources About Semiconductors

Basic Wafer Terms & Definitions
Cutting Si Wafers Off-Axis
Oxygen Precipitation in Silicon
Properties of Glass as Related to Applications with Silicon
A Guide to SEMI Specifications for Si Wafers
Wet-Chemical Etching and Cleaning of Silicon


Advertisement

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s